ep610 ? 2013 rochester electronics, llc. all rights reserved 04112013 specifcation number ep610-ci (at) rev - page 1 of 9 rochester electronics guarantees performance of its semiconductor products to the original oem specifcations. typical values are for reference purposes only. certain minimum or maximum ratings may be based on product characterization, design, simulation, or sample testing. rochester electronics reserves the right to make changes without further notice to any specifcation herein. for complete rochester ordering guide, please refer to page 2 please contact factory for specifc package availability and military/aerospace specifcations/availability. features figure 1. ep610 package pin-out diagrams package outlines not drawn to scale. windows in ceramic packages only. high-performance, 16-macrocell classic epld - combinatorial speeds with t pd as low as 10 ns - counter frequencies of up to 100 mhz - pipelined data rates of up to 100 mhz p rogrammable i/o architecture with up to 20 inputs or 16 outputs and 2 clock pins t he following devices are pin-, function-, and programming fle-compatible: ep610, ep610i, ep610t, ep610-xx/b, ep600i, and palce610 p rogrammable clock option for independent clocking of all registers m acrocells individually programmable as d, t, jk, or sr fipfops, or for combinatorial operation a vailable in windowed ceramic and one-time-programmable (otp) plastic packages (see figure 1): - 24-pin small-outline integrated circuit (plastic soic only) - 24-pin dual in-line package (cerdip and pdip) - 28-pin plastic j-lead chip carrier (plcc) clk1 input i/o i/o i/o i/o i/o i/o i/o i/o input gnd clk1 input i/o i/o i/o i/o i/o i/o i/o i/o input gnd 24 23 22 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 5 6 7 8 9 10 11 25 24 23 22 21 20 19 vcc input i/o i/o i/o i/o i/o i/o i/o i/o input clk2 i/o input clk1 vcc vcc input i/o i/o i/o i/o i/o i/o i/o nc i/o i/o i/o i/o i/o i/o nc i/o input gnd gnd clk2 input i/o 24 23 22 21 20 19 18 17 16 15 14 13 vcc input i/o i/o i/o i/o i/o i/o i/o i/o input clk2 24-pin soic ep610 ep610t ep610 ep610t ep610i ep610 ep610t ep610-xx/b ep610i 24-pin dip 28-pin j-lead 4 3 2 1 28 27 26 12 13 14 15 16 17 18 1 ? 2 3 4 5 6 7 8 9 10 11 12
page 2 of 9 rochester part number altera part number package temperature ep610dc-25 ep610dc-25 cdip-24 0 to +70c ep610dc-30 ep610dc-30 cdip-24 0 to +70c ep610dc-35 ep610dc-35 cdip-24 0 to +70c ep610di-30 ep610di-30 cdip-24 -40 to +85c ep610di-35 ep610di-35 cdip-24 -40 to +85c ep610dm-35 ep610dm-35 cdip-24 -55 to +125c ep610dm/b ep610dm883b cdip-24 -55 to +125c ep610jc-25 ep610jc-25 ldcc-28, ceramic 0 to +70c ep610jc-30 ep610jc-30 ldcc-28, ceramic 0 to +70c ep610jc-35 ep610jc-35 ldcc-28, ceramic 0 to +70c ep610ji-30 ep610ji-30 ldcc-28, ceramic -40 to +85c ep610ji-35 ep610ji-35 ldcc-28, ceramic -40 to +85c ep610jm-35 ep610jm-35 ldcc-28, ceramic -55 to +125c ep610jm-40 ep610jm-40 ldcc-28, ceramic -55 to +125c ep610lc-15 ep610lc-15 ldcc-28, plastic 0 to +70c ep610lc-20 ep610lc-20 ldcc-28, plastic 0 to +70c ep610lc-25 ep610lc-25 ldcc-28, plastic 0 to +70c ep610lc-30 ep610lc-30 ldcc-28, plastic 0 to +70c ep610li-20 ep610li-20 ldcc-28, plastic -40 to +85c ep610li-30 ep610li-30 ldcc-28, plastic -40 to +85c EP610LI-35 EP610LI-35 ldcc-28, plastic -40 to +85c ep610pc-15 ep610pc-15 pdip-24 0 to +70c ep610pc-20 ep610pc-20 pdip-24 0 to +70c ep610pc-25 ep610pc-25 pdip-24 0 to +70c ep610pc-30 ep610pc-30 pdip-24 0 to +70c ep610pc-35 ep610pc-35 pdip-24 0 to +70c ep610pi-30 ep610pi-30 pdip-24 -40 to +85c ep610pi-35 ep610pi-35 pdip-24 -40 to +85c ep610sc-15 ep610sc-15 sop-24, plastic 0 to +70c ep610sc-20 ep610sc-20 sop-24, plastic 0 to +70c ep610sc-25 ep610sc-25 sop-24, plastic 0 to +70c ep610sc-30 ep610sc-30 sop-24, plastic 0 to +70c rochester ordering guide *most products can also be offered as rohs compliant, designated by a Cg suffx. please contact factory for more information. ep610 specifcation number ep610-ci (at) rev -
page 3 of 9 table 1 summarizes ep610 device features table 1. ep610 device features feature ep610 ep610t ep610-xx/b ep610i t pd 15 ns 15 ns 35 ns 10 ns counter frequency 83 mhz 83 mhz 28.5 mhz 100 mhz pipeline data rates 83 mhz 83 mhz 37 mhz 100 mhz packages 24-pin soic 24-pin cerdip 24-pin pdip 24-pin plcc 24-pin soic 24-pin pdip 28-pin plcc 24-pin cerdip 24-pin cerdip 24-pin pdip 28-pin plcc general description figure 2. ep610 block diagram numbers without parentheses are for dip and soic packages. numbers in parentheses are for j-lead packages. ep610 devices have 16 macrocells, 4 dedicated input pins, 16 i/o pins, and 2 global clock pins (see figure 2). each macrocell can access signals from the global bus, which consists of the true and complement forms of the dedicated inputs and the true complement forms of either the output of the macrocell of the i/o input. clk1 is a dedicated clock input for the registers in macrocells 9 through 16. clk2 is a dedicated clock input for registers in macrocells 1 through 8. 2 (3) input 1 (2) clk1 3 (4) 4 (5) 5 (6) 6 (7) 7 (8) 8 (9) 9 (10) 10 (12) 11 (13) input input 23 (27) clk2 13 (16) 22 (26) 21 (25) 20 (24) 19 (23) 18 (22) 17 (21) 16 (20) 15 (18) input 14 (17) global bus macrocell 9 macrocell 10 macrocell 11 macrocell 12 macrocell 13 macrocell 14 macrocell 15 macrocell 16 macrocell 9 macrocell 10 macrocell 11 macrocell 12 macrocell 13 macrocell 14 macrocell 15 macrocell 16 ep610 specifcation number ep610-ci (at) rev -
page 4 of 9 absolute maximum ratings recommended operating conditions ep610 ep610t ep610-xx/b ep610i symbol parameter conditions min max min max unit v cc supply voltage with respect to gnd -2.0 7.0 -2.0 7.0 v v i dc input voltage -2.0 7.0 -0.5 v cc + 0.5 v i max dc v cc or gnd current -175 175 ma i out dc output current, per pin -25 25 ma p d power dissipation 1000 mw t stg storage temperature no bias -65 150 -65 150 c t amb ambient temperature under bias -65 135 (125) -10 85 c t j junction temperature under bias (150) c ep610 ep610t ep610-xx/b ep610i symbol parameter conditions min max min max unit v cc supply voltage 4.75 (4.5) 5.25 (5.5) 4.75 5.25 v v i input voltage 0 v cc 0 v cc v v o output voltage 0 v cc 0 v cc v t a operating temperature for commerical use 0 70 0 70 c t a operating temperature for industrial use -40 85 -40 85 c t c case temperature for military use -55 125 c t r input rise time 100 (50) 500 ns t f input fall time 100 (50) 500 ns recommended operating conditions symbol parameter conditions min typ max unit v ih high-level input voltage 2.0 v cc + 0.3 v v il low-level input voltage -0.3 0.8 v v oh high-level ttl output voltage i oh = -4 ma dc 2.4 v v oh high-level cmos output voltage i oh = -2 ma dc 3.84 v v ol low-level output voltage i ol = 4 ma dc 0.45 v i i input leakage output v i = v cc or gnd -10 10 a i oz tri-state output leakage current v o = v cc or gnd -10 10 a ep610 specifcation number ep610-ci (at) rev -
page 5 of 9 capacitance ep610 ep610t ep610-xx/b ep610i symbol parameter conditions min max min max min max unit c in input pin capacitance v in = 0 v, f = 1.0 mhz 10 20 8 pf c i/o i/o pin capacitance v out = 0 v, f = 1.0 mhz 12 20 8 pf c clk1 clk1 pin capacitance v in = 0 v, f = 1.0 mhz 20 20 10 pf c clk2 clk2 pin capacitance v in = 0 v, f = 1.0 mhz 20 20 12 pf i cc supply current: ep610 & ep610t i cc supply current: ep610-xx/b & ep610i ep610 ep610t symbol parameter conditions speed grade min typ max min typ max unit i cc1 v cc supply current (non-turbo, standby) v i = v cc or gnd, no load 20 150 a i cc2 v cc supply current (non-turbo, active) v i = v cc or gnd, no load, f = 1.0 mhz 5 10 (15) m a i cc3 v cc supply current (turbo, active) -15, -20 60 90 (115) 60 90 ma -25, -30, -35 45 60 (75) 60 90 ma ep610-xx/b ep610i symbol parameter conditions min typ max min typ max unit i cc1 v cc supply current (non-turbo, standby) v i = v cc or gnd, no load 900 20 150 a i cc2 v cc supply current (non-turbo, active) v i = v cc or gnd, no load, f = 1.0 mhz 25 3 8 m a i cc3 v cc supply current (turbo, active) v i = v cc or gnd, no load, f = 1.0 mhz 140 65 105 ma ep610 specifcation number ep610-ci (at) rev -
page 6 of 9 ac operating conditions: ep610-15 & ep610-20 ep610-15 ep610-15t ep610-20 ep610-20t non-turbo adder symbol parameter conditions min max min max unit t pd1 input to non-registered output c1 = 35 pf 15 20 20 ns t pd2 i/o input to non-registered output c1 = 35 pf 17 22 20 ns t pzx input to output enable c1 = 35 pf 15 20 20 ns t pxz input to output disable c1 = 5 pf 15 20 20 ns t clr asynchronous output clear time c1 = 35 pf 15 20 20 ns t io i/o input pad and buffer delay 2 2 0 ns f max maximum clock frequency 83.3 62.5 0 mhz t su global clock input setup time 9 11 20 ns t h global clock input hold time 0 0 0 ns t ch global clock high time 6 8 0 ns t cl global clock low time 6 8 0 ns t co1 global clock to output delay 11 13 0 ns t cnt global clock minimum period 12 16 0 ns f cnt global clock internal maximum frequency 83.3 62.5 0 mhz t asu array clock input setup time 6 8 20 ns t ah array clock input hold time 6 8 0 ns t ach array clock high time 7 9 0 ns t acl array clock low time 7 9 0 ns t aco1 array clock to output delay 15 20 20 ns t acnt array clock minimum period 14 18 0 ns f acnt array clock internal maximum frequency 71.4 55.6 0 mhz ep610 specifcation number ep610-ci (at) rev -
page 7 of 9 ac operating conditions: ep610-15 & ep610-20 note (1) ep610-25 ep610-25t ep610-20 ep610-20t ep610-35 non- turbo adder symbol parameter conditions min max min max min max unit t pd1 input to non-registered output c1 = 35 pf 25 30 35 30 ns t pd2 i/o input to non-registered output 27 32 37 30 ns t pzx input to output enable 25 30 35 30 ns t pxz input to output disable c1 = 5 pf note (2) 25 30 35 30 ns t clr asynchronous output clear time c1 = 35 pf 27 32 37 30 ns t io i/o input pad and buffer delay 2 2 2 0 ns f max maximum clock frequency note (3) 47.6 41.7 37.0 0 mhz t su global clock input setup time 21 24 27 30 ns t h global clock input hold time 0 0 0 0 ns t ch global clock high time 10 11 12 0 ns t cl global clock low time 10 11 12 0 ns t co1 global clock to output delay 15 17 20 0 ns t cnt global clock minimum period 25 30 35 0 ns f cnt global clock internal maximum frequency note (4) 40.0 33.3 28.6 0 mhz t asu array clock input setup time 8 8 8 30 ns t ah array clock input hold time 12 12 12 0 ns t ach array clock high time 10 11 12 0 ns t acl array clock low time 10 11 12 0 ns t aco1 array clock to output delay 27 32 37 30 ns t acnt array clock minimum period 25 30 35 0 ns f acnt array clock internal maximum frequency note (4) 40.0 33.3 28.6 0 mhz notes to tables: (1) operating conditions: v cc = 5 v 5%, t a = 0 c to 70 c for commercial use. v cc = 5 v 10%, t a = -40 c to 85 c for industrial use. v cc = 5 v 10%, t c = -55 c to 125 c for military use. (2) sample-tested only for an output change of 500 mv. (3) the f max values represent the highest frequency for pipelined data. (4) measured with a device programmed as a 16-bit counter. i cc measured at 0 c. ep610 specifcation number ep610-ci (at) rev -
page 8 of 9 ac operating conditions: ep610-xx/b note (1) symbol parameter conditions min max unit t pd1 input to non-registered output c1 = 35 pf notes (2), (3) 35 ns t pd2 i/o input to non-registered output 37 ns t pzx input to output enable 35 ns t pxz input to output disable c1 = 5 pf notes (2), (3), (4), (5) 35 ns t clr asynchronous output clear time c1 = 35 pf notes (2), (3) 37 ns f max maximum clock frequency note (2), (6), (7) 37.0 mhz t su global clock input setup time note (2), (3) 27 ns t h global clock input hold time note (3) 0 ns t ch global clock high time note (4) 12 ns t cl global clock low time note (4) 12 ns t co1 global clock to output delay 20 ns t cnt global clock minimum period note (4), (8) 35 ns f cnt global clock internal maximum frequency note (8) 28.5 mhz t asu array clock input setup time notes (2), (3), (4) 8 ns t ah array clock input hold time notes (2), (3), (4) 12 ns t ach array clock high time notes (3), (4) 12 ns t acl array clock low time notes (3), (4) 12 ns t aco1 array clock to output delay notes (2), (3) 37 ns t acnt array clock minimum period notes (4), (8) 35 ns f acnt array clock internal maximum frequency notes (4), (8) 28.6 mhz notes to tables: (1) screening and characterization of ac delay parameters are conducted at 10 mhz or less. operating conditions: v cc = 5 v 10%, t c = -55 c to 125 c for military use. (2) all array-dependent delays are specifed for an xor pattern. this pattern includes two product terms and two pure inputs; all other product terms in the macrocell are held low by one eprom cell. other patterns may result in longer delays. delays for patterns involving only one product term (such as t pxz ) are specifed for an xor pattern in which only one pure input switches at a time. (3) when the turbo bit is not set (non-turbo mode), a non-turbo adder of 30 ns (maximum) is added to this parameter to determine worst-case timing. parameters may not be tested in non-turbo mode, but are guaranteed to the limits specifed. devices operating in non-turbo mode require one input or i/o transition to guarantee that the device will enter the correct power-up state. (4) these parameters may not be tested, but are guaranteed to the limits specifed in the table under absolute maximum ratings on page 3. (5) not tested directly, but guaranteed by testing t pd . (6) the f max values represent the highest frequency for pipelined data. (7) not tested directly, but derived from t su . (8) specifed with device programmed as a 16-bit counter with no output loading. ep610 specifcation number ep610-ci (at) rev -
page 9 of 9 ac operating conditions: ep610i note (1) ep610i-10 ep610i-15 ep610i-25 non-turbo adder symbol parameter min max min max min max unit t pd1 input to non-registered output, note (2) 10 15 25 25 ns t pd2 i/o input to non-registered output, note (2) 10 15 25 25 ns t pzx input to output enable 15 18 25 25 ns t pxz input to output disable, note (3) 13 18 25 25 ns t clr asynchronous output clear time 13 18 25 25 ns f max maximum clock frequency 111 83.3 66 0 mhz t su global clock input setup time 7 12 15 25 ns t h global clock input hold time 0 0 0 0 ns t ch global clock high time 5 6 7.5 0 ns t cl global clock low time 5 6 7.5 0 ns t co1 global clock to output delay 6.5 8 10 0 ns t cnt global clock minimum period 10 15 25 25 ns f cnt global clock internal maximum frequency, note (4) 100 66 40 0 mhz t asu array clock input setup time 2 4 5 25 ns t ah array clock input hold time 3 6 8 0 ns t ach array clock high time 5 7.5 10 0 ns t acl array clock low time 5 7.5 10 0 ns t aco1 array clock to output delay 12 16 25 25 ns t acnt array clock minimum period, note (4) 10 15 25 25 ns f acnt array clock internal maximum frequency, note (4) 100 66 40 0 mhz notes to tables: (1) operating conditions: v cc = 5 v 5%, t a = 0 c to 70 c for commercial use. v cc = 5 v 10%, t a = -40 c to 85 c for industrial use. (2) measured with eight outputs switching. (3) sample-tested only for an output change of 500 mv. (4) measured with a device programmed as a 16-bit counter. rochester electronics guarantees performance of its semiconductor products to the original oem specifcations. typical values are for reference purposes only. certain minimum or maximum ratings may be based on product characterization, design, simulation, or sample testing. rochester electronics reserves the right to make changes without further notice to any specifcation herein. ep610 specifcation number ep610-ci (at) rev -
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